Output buffer with switchable output impedance
US7479799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2006 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Apr 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/094
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.