PLL with dual edge sensitivity
US7479815B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2006 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Mar 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A divider apparatus for use within a phase-locked loop having an output terminal at which an output frequency is produced. The apparatus includes a prescalar circuit configured to produce a prescaled signal by dividing the output frequency in response to a mode select signal. A first programmable counter is disposed to receive the prescaled signal and to produce the mode select signal. In addition, a second programmable counter is disposed to receive the prescaled signal and to produce a divided signal utilized by the phase-locked loop. The apparatus further includes a control circuit connected to the first programmable counter and to the second programmable counter, the control circuit providing a first resynchronization signal to the first programmable counter and a second resynchronization signal to the second programmable counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.