Generating multiple delayed signals of different phases from a reference signal using delay locked loop (DLL)
US7479816B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2005 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Oct 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay elements and a duty cycle correction circuit (DCC). The lock detector, the dummy delay elements and the delay control circuit are used in a path parallel to the delay elements which generate the desired delayed signals having different delays in relation to the reference signal. Due to the use of the parallel path, the throughput performance of the DLL circuit is not impeded. In an embodiment, separate charge pumps are used by a phase comparator and the lock detector used in the parallel path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.