Cascode circuit and semiconductor device
US7479821B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Jun 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/345
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A reference voltage circuit having a high power supply rejection ratio, and can operate at low voltage is provided. The reference voltage circuit includes a bias circuit constructed such that a depletion type transistor (3) is connected in series to a power supply voltage supply terminal of a load circuit, an enhancement type MOS transistor (4) for detecting current through the load circuit to operate as a current source is connected to the load circuit, a depletion type MOS transistor (5) is connected in series to the transistor (4), and a gate terminal of the transistor (5) is connected to a source terminal of the transistor (5), in which the gate terminal of the depletion type transistor (3) is connected to the source terminal of the depletion type transistor (5).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.