Analogue self-calibration method and apparatus for low noise, fast and wide-locking range phase locked loop
US7479834B2 · kind B2 · utility
4Cited by
7References
23Claims
0Family size
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Key dates
| Filing date | Feb 4, 2005 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Apr 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/05
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop (PLL) frequency synthesizer includes a reconfigurable voltage controlled oscillator (VCO) with three modes of operation: a Linear-High-gain, Zero-gain, and Low-gain mode. During the linear high gain mode, the VCO enables an analogue self-calibration of the PLL over a wide frequency tuning range. Control voltage at the input of the VCO is varied by the PLL to provide an output frequency. When the PLL is locked, the VCO is switched to the Zero-gain mode while maintaining the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.