Comparator architecture
US7479915B1 · kind B1 · utility
6Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Dec 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator presents a linear load to input signals when providing a comparison output of two input signals. The comparator contains a transistor configured in a source/emitter follower configuration, and operates in the saturation region for substantially the entire range of strengths of the input signals. As a result, the comparator presents a substantially constant load to the input signals. When incorporated in circuits such as a pipeline ADC, the comparator may substantially eliminate errors due to non-linear loads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.