Methods and apparatus for controlling ethernet packet transfers between clock domains
US7480282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A transport circuit is described for generating enable signals in different independent clock domains enabling data transfers across the clock domains. The transport circuit is used, for example, in an Ethernet receive interface where data is to be transferred from a receive clock domain to a system core clock domain for further processing. A serial to parallel data converter is used to convert the serial Ethernet data into parallel form. The output of the serial to parallel data converter is transferred to a holding register in the receive clock domain. The holding register connects to a transfer data register that is in the system core clock domain. The transport circuit provides enable signals with the proper timing to allow the transfer of data from the receive clock domain to the system core clock domain. The last data transfer swaps the interface supplied data with a status word in the holding register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.