Software state replay
US7480610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2005 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Jul 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tool for emulation systems that obtains the state values for only discrete partitions of a circuit design. When a partition is being emulated, the emulation system obtains the input values for the specified partition at each clock cycle and the state values for the specified partition at intervals. Using the state and input values with a software model of the specified circuit design partition, the tool calculates the state values for the partition at every clock cycle. The software model may correspond to the partitioning information used to implement the circuit design across multiple configurable logic element devices, such as FPGAs. Thus, each software model may correspond to the portion of a circuit design emulated on a discrete FPGA integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.