Trap mode register
US7480755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2004 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Sep 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.