Parallel processing device and parallel processing method
US7480785B2 · kind B2 · utility
12Cited by
14References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2004 |
| Grant date | Jan 20, 2009 |
| Priority date | — |
| Expiry date | Sep 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row decoding circuit (171) outputs a select signal to a row set in a row range setting unit (172) to select a select signal line (103), processing results from processing circuits (102) on this row are output to a data output line (104), and a row adder (106) adds processing results output to a data output line (104) of a column set in a column range selector (105).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.