Gain normalization of a digitally controlled oscillator in an all digital phase locked loop based transmitter
US7482883B2 · kind B2 · utility
3Cited by
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16Claims
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Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Dec 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.