MIM capacitor in a copper damascene interconnect
US7483258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Sep 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.