Method and system for flexible network processor scheduler and data flow
US7483429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Apr 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/58
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.