Single chip GSM/EDGE transceiver architecture with closed loop power control
US7483678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Feb 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.