Correlation architecture for use in software-defined radio systems
US7483933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Jul 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70711
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a−b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and −1 and 2) the difference (a−b) multiplied by one of +1 and −1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.