Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)
US7484076B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Mar 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positive integer, the instruction being issued based on a first clock having a first clock rate, operating Q execution units to achieve the P executions of the instruction, Q being a positive integer less than P and greater than one, each of the execution units being operated based on a second clock having a second clock rate higher than the first clock rate of the first clock, and wherein the second clock rate of the second clock is equal to the first clock rate of the first clock multiplied by the ratio P/Q.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.