Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering
US7484078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Dec 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3871
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages (10c,d) are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned (10c,d) requires writing. A write sequencing circuit (144) performs write tests alternately for instruction dependent information in the first and second one of the stages (10c,d). When the write sequencing circuit (144) performs the write test for a particular one of the stages (10c,d), it tests whether the instruction dependent information in the particular one of the stages (10c,d) requires writing of a result. If so, the write sequencing circuit (144), delays transfer of new instruction dependent information through the pipeline (10a-d) to the particular one of the stages (10c,d) un…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.