Method to optimize the manufacturing of interconnects in microelectronic packages
US7484190B1 · kind B1 · utility
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3References
1Claims
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Key dates
| Filing date | Apr 15, 2008 |
| Grant date | Jan 27, 2009 |
| Priority date | — |
| Expiry date | Apr 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2113/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing the manufacturing of interconnects in microelectronic packages in the presence of sources of process variability. The method can estimate the contribution of multiple parameter to the quality of the interconnects, enabling the optimization of the manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.