Semiconductor memory device
US7485935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2007 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Aug 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines. The plate voltage supply lines are composed of a material having a resistance lower than that of the plate lines, each of capacitors of the plural memory cells is covered with a hydrogen barrier film HB at its periphery, the plural plate voltage supply lines are disposed beneath the hydrogen barrier film HB, and the plural plate voltage supply lines CPS are, when viewed in a plane, electrically connected to the same plate line at plural positions of the same plate line, within a region where the hydrogen barrier film is disposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.