Programmable logic devices comprising time multiplexed programmable interconnect
US7486111B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | May 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Time-multiplexed interconnect structures, timing optimization techniques and software tools for said structures, for programmable semiconductor ICs is disclosed. A first aspect is a programmable logic device, wherein a plurality of outputs from logic blocks is coupled to a plurality of inputs to logic blocks by a single wire segment comprising a programmable time multiplexing method. A second aspect is a software placement and route tool, wherein a plurality of routs is assigned to a single route, wherein the plurality of routs is routed in the single route by a time multiplexed method. A third aspect is a critical signal propagation path in a programmable logic device comprising global non-overlapping control signals and time multiplexed wires, wherein each control signal assigns a programmable time slot for multiple signals within one of said wires, further comprising one or more critical signals assigned to the last multiplexed time slot.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.