High-rate RLL encoding
US7486208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2007 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | May 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/956
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An unencoded m-bit data input sequence is divided into a block of n bits and a block of m−n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.