Nano-liquid crystal on silicon (LCOS) chip having reduced noise
US7486287B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 15, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Jul 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136218
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An LCoS chip is designed to suppress electrical noise due to cross-talk between electrical components of the chip and stray light entered into the chip. The LCoS chip includes a silicon substrate having an array of memory cells formed the substrate. The chip includes a first polycrystalline silicon layer that forms word lines and a metal layer that forms bit lines, wherein bit lines are directed orthogonal to the word lines. The chip also includes capacitor storages formed on second and third second polycrystalline silicon layers. The second polycrystalline layer is disposed over the first polycrystalline silicon layer and over regions of the substrate not covered by the word lines. The metal layer includes shields to reduce cross-talk between neighboring bit lines as well as between the bit lines and the capacitor storages. A third polycrystalline layer is configured to reduce cross-talk between the bit lines and the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.