Multi-slice network processor
US7486678B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2003 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Apr 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.