Alignment of clock signal with data signal
US7486752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Sep 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A received clock signal is aligned (“eye centered”) with a received data signal by recovering a separate clock from the data signal and comparing and aligning the received clock with the recovered clock by delaying one or both of the received clock and the received data as necessary. After the necessary delays are set, the comparison/alignment circuitry can be turned off, until the next time alignment is necessary, to conserve power. In a multiple channel system, any combination of each received data channel, the received clock, or individual branches of the received clock in each channel can be delayed as necessary. Each channel can have its own comparison/alignment circuitry so that all channels can be aligned simultaneously, or re-usable circuitry can be provided for connection sequentially to each channel where sequential alignment of the channels is fast enough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.