System clock distributing apparatus and system clock distributing method
US7486754B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 28, 2005 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Aug 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a system clock distributing apparatus and a system clock distributing method for reducing a skew of a system clock and a synchronizing signal at low cost. The system clock distributing apparatus for matching the timing of data by using the synchronizing signal includes an oscillator 1 that generates a periodical synchronizing signal and a PLL 2, a memory that stores the data, at least one CPU 13 that conducts a computing process using the data stored in the memory, at least one MAC 14 that controls an access from the CPU 13 to the memory, and at least one NB 12 that generates the system clock having a frequency that is an integral multiple of the synchronizing signal, and controls the CPU 13 and the MAC 14 based on the operation by the system clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.