Receiver for PMD mitigation by polarization scrambling
US7486898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 2005 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Feb 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/2572
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver (10) for an optical signal containing a time jitter and a time-varying distortion caused by a periodic polarization scrambled signal comprises at least one decision gate (11) and a clock recovery module (13) providing a clock signal (C) recovered from the optical signal to the at least one decision gate (11). The receiver (10) further comprises a scrambling frequency generator (16) synchronized to the scrambling frequency and phase of the polarization scrambled signal, a jitter function generator (17) generating a clock phase control signal (Δφb) reproducing the time jitter, and at least one clock phase modulator (14) modulating the phase of the clock signal (C) according to the clock phase control signal (Δφb).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.