Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource
US7487341B2 · kind B2 · utility
31Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a method for communicating a request for handling of a fault or exception occurring in an accelerator to a first instruction sequencer coupled thereto. The accelerator may be a heterogeneous resource with respect to the first instruction sequencer, e.g., of a different instruction set architecture. Responsive to the request, the fault or exception may be handled in the first instruction sequencer. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.