Semiconductor integrated circuit and method for testing same
US7487418B2 · kind B2 · utility
8Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2003 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Jun 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An LSI which makes scan testing possible without compromising security is provided. Flip-flops that constitute a scan chain are reset when scan testing is initiated or terminated by the edges of a mode signal for switching between normal operations and scan testing. In addition, during scan testing, internal memory means is made inaccessible. Further, a dummy flip-flop that operates only during scan testing is connected to the scan chain, and shifting out by the scan chain during normal operations is made impossible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.