Enabling netlist for modeling of technology dependent BEOL process variation
US7487473B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Mar 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and program product are disclosed that enable a netlist of an integrated circuit (IC) design for modeling of technology dependent back-end-of-line (BEOL) process variation. In one embodiment, the method includes obtaining a netlist of electrical elements (i.e., BEOL parasitic resistance and/or capacitance), the netlist including estimated electrical values for the electrical elements and geometric data for at least one of the electrical elements; determining variations of the electrical value for a selected electrical element based on the geometric data using a scaling methodology; and placing a model call in the netlist, the model call implementing the variations of electrical value for the selected electrical element. The revised netlist can be used to model the IC design and includes a scaling of electrical values without having to generate more than one netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.