Parametric-based semiconductor design
US7487477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Feb 3, 2009 |
| Priority date | — |
| Expiry date | Jul 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parametric-based design methodology interlocks the design of library elements used in a semiconductor product design with the testing protocol used for the resulting semiconductor products such that parametric assumptions made regarding library elements used in a semiconductor product design may be used to disposition products such as semiconductor chips incorporating a semiconductor product design. In particular, a parametric measurement element is incorporated into a product design along with one or more library elements, with the parametric measurement element used to test one or more parametric design points that are associated with the library elements when the product design is used in a manufactured product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.