Method for preparing 2-dimensional semiconductor devices for integration in a third dimension
US7488630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2007 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Apr 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.