Semiconductor integrated circuit device and I/O cell for the same
US7488995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Aug 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit device in which a plurality of I/O cells having level shift circuits are placed in an I/O region, two input/output cells respectively have four level shift circuits 11, 12a to 12c. A power supply cell, originally including only wiring for supply of a power supply voltage or a ground voltage, is additionally provided with three level shift circuits, which should originally be placed in the two input/output cells. The level shift circuits in the power supply cell are circuits asked for no high-speed operation and shared by the two input/output cells. This reduces the size of the two input/output cells and reduces the pitch of the I/O cells, permitting a larger number of required pins in a smaller area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.