Stacked semiconductor device
US7489030B2 · kind B2 · utility
24Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Aug 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.