VCO buffer circuit
US7489205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2005 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Sep 12, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.