Methods for reducing write time in nonvolatile memory devices and related devices
US7489557B2 · kind B2 · utility
9Cited by
2References
36Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 27, 2007 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a non-volatile memory device includes maintaining a write voltage at a predetermined voltage level for programming and/or erasing a memory cell of the non-volatile memory device during a time between execution of consecutive write operations. For example, the write voltage may be activated at the predetermined voltage level responsive to an initial write command, and discharge of the write voltage may be prevented responsive to a signal indicating consecutive write commands. Related devices are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.