High performance, low-leakage static random access memory (SRAM)
US7489584B2 · kind B2 · utility
6Cited by
11References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 11, 2005 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | May 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses a memory array system operative to store data bits in individually addressable rows and columns. The memory array system comprises a plurality of memory blocks, each of the plurality of memory blocks having a plurality of memory rows and a row peripheral circuit operative to switch a memory block from a retention mode to an activation mode in response to an addressing of a memory row within the memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.