Architecture for compact multi-ported register file
US7490208B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2004 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Oct 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/372
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Architecture for compact multi-ported register file is disclosed. In an embodiment, a register file comprises a single-port random access memory (RAM). The single-port RAM comprises a single port for read operations and for write operations. Either a single read or a single write operation is performed for a given clock via the single port. Moreover, the single-port RAM serially performs N read operations and M write operations associated with a data group using a clock phase of (N+M) clock phases generated from a clock. In another embodiment, a semiconductor device includes the architecture for compact multi-ported register file. The semiconductor device comprises a plurality of register files. Each register file comprises a RAM comprising a port for read operations and for write operations. Moreover, each RAM serially performs N read operations and M write operations associated with one of a plurality of data groups using a corresponding clock phase of (N+M) clock phases generated from a clock. Further, the semiconductor device comprises an input staging unit for staging write data of one or more of the write operations. Continuing, the semiconductor device comprises an output st…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.