PCI express physical layer built-in self test architecture
US7490278B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | May 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03866
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A built-in self test circuit includes a first pattern generator, an elastic buffer receiver, a command symbol detector, a second pattern generator, and a logic unit. The architecture is capable of compensating loopback latency automatically without having to utilize a device that stores test patterns generated by the first pattern generator, and error warning can be greatly reduced. Also, the architecture can reduce the effect of phase jitter and error rate count is provided. Hence, accuracy of test can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.