Test interface for random access memory (RAM) built-in self-test (BIST)
US7490279B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2005 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Built-In Self Test (BIST) is a test technique wherein semiconductor integrated circuit devices test themselves during their operation lifetime. BIST techniques do not necessarily require additional hardware; they can be implemented using dedicated software routines. Various BIST algorithms and techniques have been proposed for testing random access memory (RAM) devices. The present invention provides an architecture for the memory-test interface that allows the serial transfer of the test background data from the BIST controller to the interface of the memory-under-test using a single bit with serial-to-parallel data conversion using a shift register in the memory interface. The size of the shift register is equal to the word width of the memory-under-test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.