Sub-system power noise suppression design procedure
US7490306B2 · kind B2 · utility
3Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2006 |
| Grant date | Feb 10, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure provide methods and systems to design a distributed discrete capacitor bank incorporating power plane capacitance to concentrate the suppression of AC coupling to the frequencies caused by clocks and signal transitions. Aspects of the disclosure provide a procedure for designing a distributed capacitor bank from a combination of bulk capacitors, ceramic capacitors and/or plane capacitance that provides the desired impedance Z to suppress noise at all desired frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.