Semiconductor integrated circuit arrangement device and method
US7490985B2 · kind B2 · utility
0Cited by
14References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 16, 2005 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Dec 16, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An arrangement device including: a photography section, which photographs a first mark and a second mark in a state in which a semiconductor integrated circuit to which the first mark is applied and a member to which the second mark is applied, which member is to be used in combination with the semiconductor integrated circuit, overlap; and a movement section, which relatively moves at least one of the semiconductor integrated circuit and the member with respect to the other thereof on the basis of positions of the first mark and the second mark which have been photographed by the photography section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.