Design structure for high speed differential receiver with an integrated multiplexer input
US7492191B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2007 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Oct 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.