Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling
US7492296B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Sep 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/486
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled using one or more reference capacitor(s) that have been charged with a net charge corresponding to a quantizer-controlled reference voltage in a preceding clock phase. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high input impedance. The reference capacitor(s) may be discharged in a third clock phase, so that input-signal-dependent voltages are discharged from the capacitor(s). An additional sampling capacitor can be discharged in the first clock phase and coupled in parallel with the reference capacitor during the second clock phase, to set the gain with respect to the input voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.