Memory egress self selection architecture
US7492760B1 · kind B1 · utility
18Cited by
16References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13292
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method of time division multiplex switching reduces the implementation area by reducing the area required for both memory storage at each egress port and the multiplexing circuitry required. Ingress and egress processors are implemented to control the storage and selection of data grains to allow for the reduction in the memory and multiplexer areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.