Real-time reassembly of ATM data
US7492790B2 · kind B2 · utility
1Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Dec 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5652
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The real-time reassembly of data received over an ATM network is enabled by a system including two digital memories, an indicator for indicating one of the two memories as a process memory and another one of the two memories as a storage memory, a buffer memory, a processor which processes the digital contents of a cell stored in the process memory and stores the digital contents of a subsequent cell in the storage memory. In operation of the system, the processing of the contents of the process memory is completed prior to completion of the receiving and storing of the contents of the subsequent cell in the storage memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.