Interrupt handling using simultaneous multi-threading
US7493436B2 · kind B2 · utility
18Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Apr 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logical processor and a second logical processor associated with the at least one physical processor are partitioned. The first logical processor is assigned to manage interrupts and the second logical processor is assigned to dispatch runnable user threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.