Memory queue with supplemental locations for consecutive addresses
US7493456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2006 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Jun 6, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes an address queue with address queue locations that may expand to store address commands that point to consecutive locations in memory. In this manner, multiple address commands may combine together in a common expanded address queue location. In one embodiment, each address queue location includes a main information portion and a supplemental information portion. The supplemental information portion is smaller than the main information portion. The main information portion stores the target address information of a first address command. When the address queue receives an address command with a target address that is consecutive to the target address of the first command, then the supplemental address portion stores a subset of the target address of the second command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.