States encoding in multi-bit flash cells for optimizing error rate
US7493457B2 · kind B2 · utility
49Cited by
10References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2005 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Feb 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5628
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.