Code size reduction method through multiple load/store instructions
US7493463B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Jun 13, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/4434
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to transfer a plurality of data stored in a memory using one instruction. In a memory including at least two regions to which the addresses are assigned respectively, data are allocated to the addresses in sequence, and the allocated data are transferred using one instruction. At least one block is generated, which transfers data using one instruction, and it is instructed to include the data in the at least one block. The data in the block are linked with each other, and the number of paths linking two data is calculated with respect to the at least one block. The data are linked using shortest paths in consideration of the number of the linking paths, and the data are allocated by the addresses using the shortest paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.