Semiconductor memory device and refresh period controlling method
US7493531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2005 |
| Grant date | Feb 17, 2009 |
| Priority date | — |
| Expiry date | Aug 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.